View HI-3588PQI_1717422.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the hi-3588 from holt integrated circuits is a silicon gate cmos device for interfacing a serial peripheral interface (spi) enabled microcontroller to an arinc 429 serial bus. the device provides one receiver with user-programmable label recognition for any combination of 256 possible labels, a 32 by 32 receive fifo and an analog line receiver. receive fifo status can be monitored using the programmable external interrupt pin, or by polling the hi-3588 status register. other features include the ability to switch the bit-signifiance of arinc 429 labels. the arinc input pins are available with different input resis- tance values to provide flexibility when adding external lightning protection circuitry. the serial peripheral interface minimizes the number of host interface signals allowing for a small footprint device which can be interfaced to a wide variety of industry- standard microcontrollers supporting spi. alternatively, the spi signals may be controlled using just four general purpose i/o port pins from a microcontroller or custom fpga. the spi and all control signals are cmos and ttl compatible and support 3.3v or 5v operation. the hi-3588 checks received data against arinc 429 electrical, timing and protocol requirements. arinc 429 databus timing comes from a 1 mhz clock input, or an internal counter can derive it from higher clock frequencies having certain fixed values, possibly the external host processor clock. features arinc specification 429 compliant 3.3v or 5.0v logic supply operation directly to arinc 429 bus programmable label recognition for 256 labels 32 x 32 receive data fifo programmable high-speed, four-wire serial peripheral interface label bit-order control parity checking may be disabled to allow 32-bit data reception low power industrial & extended temperature ranges on-chip analog line receiver connects data rate selection pin configurations (top view) hi-3588 july 2009 (ds3588 rev. c) 07/09 arinc 429 receiver with spi interface 44 - pin plastic 7mm x 7mm chip-scale package (qfn) 44 - pin plastic quad flat pack (pqfp) hi-3588pci hi-3588pct 44 - n/c 43 - rina 42 - rina-40 41 - n/c 40 - vdd 39 - n/c 38 - n/c 37 - n/c 36 - n/c 35 - n/c 34 - n/c 33 - n/c 32 - n/c 31 - n/c 30 - gnd 29 - n/c 28 - n/c 27 - n/c 26 - n/c 25 - rflag 24 - n/c 23 - n/c n/c-12 n/c-13 n/c-14 sck-15 n/c-16 gnd-17 n/c-18 aclk - 19 so-20 n/c-21 n/c-22 n/c - 1 rinb-40 - 2 rinb - 3 n/c - 4 n/c - 5 n/c - 6 mr - 7 si - 8 -9 n/c-10 n/c-11 cs HI-3588PQI hi-3588pqt 44 - n/c 43 - rina 42 - rina-40 41 - n/c 40 - vdd 39 - n/c 38 - n/c 37 - n/c 36 - n/c 35 - n/c 34 - n/c n/c - 1 rinb-40 - 2 rinb - 3 n/c - 4 n/c - 5 n/c - 6 mr - 7 si - 8 -9 n/c - 10 n/c - 11 cs 33 - n/c 32 - n/c 31 - n/c 30 - gnd 29 - n/c 28 - n/c 27 - n/c 26 - n/c 25 - rflag 24 - n/c 23 - n/c n/c - 12 n/c - 13 n/c - 14 sck - 15 n/c - 16 gnd - 17 n/c - 18 aclk - 19 so - 20 n/c - 21 n/c - 22 holt integrated circuits www.holtic.com
block diagram pin descriptions signal function description pull up / down rinb input arinc receiver negative input. direct connection to arinc 429 bus rinb-40 input alternate arinc receiver negative input. requires external 40k ohm resistor mr input master reset. a positive pulse clears the receiver data fifo and flags 10k ohm pull-down si input spi interface serial data input 10k ohm pull-down input chip select. data is shifted into si and out of so when is low. 10k ohm pull-up sck input spi clock. data is shifted into or out of the spi interface using sck 10k ohm pull-down gnd power chip 0v supply. note both gnd pins must be connected aclk input master timing source for the arinc 429 receiver 10k ohm pull-down so output spi interface serial data output rflag output goes high when arinc 429 receiver fifo is empty (cr15=0), or full (cr15=1) vdd power 3.3v or 5.0v logic power rina-40 input alternate arinc receiver positive input. requires external 40k ohm resistor rina input arinc receiver positive input. direct connection to arinc 429 bus cs cs vdd spi interface control register status register arinc 429 received data fifo label filter arinc 429 valid word checker arinc 429 line receiver label filter bit map memory rina-40 rina rinb rinb-40 sck cs si so rflag aclk gnd 40 kohm 40 kohm arinc clock divider hi-3588 holt integrated circuits 2
example: one spi instruction op code 07hex data field 02hex msb lsb msb lsb cs sck si table 1. defined instruction op codes op code hex 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 data field none none none none 8 bits 8 bits 256 bits 8 bits 32 bits variable 8 bits 16 bits 8 bits 256 bits none none 16 bits description no instruction implemented after the 8th op-code bit is received, perform master reset (mr) , reset all label selections , set all the label selections reset label at address specified in data field set label at address specified in data field starting with label ff hex, consecutively set or reset each label in descending order for example, a data field pattern starting with 1011 will set labels ff, fd, and fc hex and reset label fe hex. programs a division of the aclk input. if the divided aclk frequency is 1 mhz and control register bit cr1 is set, the arinc receiver operates from the divided aclk clock. allowable values for division rate are x1, x2, x4, x8, or xa hex. any other programmed value results in no clock. note: aclk input frequency and division ratio must result in 1 mhz clock. read the next word in the receive fifo. if the fifo is empty, it will read zeros dump the receive fifo. no framing. if held low after last word, the data will be zeros. read the status register read the control register read the aclk divide value programmed previously using op code 07 hex read the label look-up memory table consecutively starting with address ff hex no instruction implemented write the control register after the 8th op-code bit is received after the 8th op-code bit is received no instruction implemented cs hi-3588 instructions instruction op codes are used to read, write and configure the hi- 3588a. when goes low, the next 8 clocks at the sck pin shift an instruction op code into the decoder, starting with the first positive edge. the op code is fed into the si pin, most significant bit first. for write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising sck edge. data word length varies depending on word type written: 16-bit writes to control register, 32-bit arinc word writes to transmit fifo or 256-bit writes to the label-matching enable/disable table. cs for read instructions, the most significant bit of the requested data word appears at the so pin after the last op code bit is clocked into the decoder, at the next falling sck edge. as in write instructions, data field bit-length varies with read instruction type. table 1 lists all instructions. instructions that perform a reset or set are executed after the last si bit is received while is still low. cs holt integrated circuits 3
functional description hi-3588 sr bit function state description sr0 receive fifo 0 1 receiver fifo is empty receiver fifo contains valid data (lsb) empty sets to one when all data has been read. rflag pin reflects the state of this bit when cr15=?0? sr1 receive fifo 0 receiver fifo holds less than 16 half full words 1 receiver fifo holds at least 16 words sr2 receive fifo 0 receiver fifo not full. rflag pin full reflects the state of this bit when cr15=?1? 1 receiver fifo full. to avoid data loss, the fifo must be read within one arinc word period sr3 not used x undefined sr4 not used x undefined sr5 not used x undefined sr6 not used 0 always ?0? sr7 not used 0 always ?0? (msb) cr bit function state description cr0 receiver 0 data rate = clk/10 1 data rate = clk/80 (arinc 429 high-speed) (lsb) data rate select (arinc 429 low-speed) cr1 arinc clock 0 arinc clk = aclk input frequency source select 1 arinc clk = aclk divided by the value programmed with spi instruction 07 hex cr2 enable label 0 label recognition disabled recognition 1 label recognition enabled cr3 - x not used cr4 receiver 0 receiver parity check disabled parity check enable 1 receiver odd parity check enabled cr5 receiver 0 disable receiver. the hi-3588 ignores enable all arinc 429 data bus traffic 1 normal operation cr6 receiver 0 receiver decoder disabled decoder 1 arinc bits 10 and 9 must match cr7 and cr8 cr7 - - if receiver decoder is enabled, the arinc bit 10 must match this bit cr8 - - if receiver decoder is enabled, the arinc bit 9 must match this bit cr9 - x not used cr10 - x not used cr11 arinc label 0 label bit order reversed (seetable 2) bit order 1 label bit order same as received (see table 2) cr12 - x not used cr13 - x not used cr14 - x not used cr15 rflag 0 flag goes high when receive fifo is empty (msb) definition 1 rflag goes high when receive fifo is full control word register the hi-3588 contains a 16-bit control register which is used to configure the device. control register bits cr15 - cr0 are loaded from a 16-bit data value appended to spi instruction 10 hex. the control register contents may be read using spi instruction 0b hex. each bit of the control register has the following function: status register the hi-3588 contains an 8-bit status register which can be interrogated to determine status of the arinc receive fifo. the status register is read using spi instruction 0a hex. unused bits are undefined and may be read as either ?1? or ?0?. the following table defines the status register bits. parity sdi label label (lsb) label (msb) label label label label label sdi parity sdi label label (msb) label (lsb) label label label label label sdi arinc 429 data format control register bit cr11 controls how individual bits in the received arinc word are mapped to the hi-3588 spi data word bits during data read or write operations. the following table describes this mapping: table 2. spi / arinc bit-mapping spi 1 2-22 23242526272829303132 order . arinc bit 32 31 - 11 10 912345678 cr11=0 data arinc bit 32 31 - 11 10 987654321 cr11=1 data holt integrated circuits 4
ister, a low bit is clocked. only one shift register can clock a high bit for any given sample. all three registers clock low bits if the differential input voltage is between defined state voltage bands. valid data bits require at least three consecutive one or zero samples (three high bits) in the upper half of the ones or ze- ros sampling shift register, and at least three consecutive null samples (three high bits) in the lower half of the null sampling shift register within the data bit interval. a word gap null requires at least three consecutive null sam- ples (three high bits) in the upper half of the null sampling shift register and at least three consecutive null samples (three high bits) in the lower half of the null sampling shift reg- ister. this guarantees the minimum pulse width. 3. to validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. with exactly 1mhz input clock frequency, the acceptable data bit rates are: 83k bps 10.4k bps 125k bps 15.6k bps 4. following the last data bit of a valid reception, the word gap timer samples the null shift register every 10 input clocks (every 80 clocks for low speed). if a null is present, the word gap counter is incremented. a word gap count of 3 enables the next reception. the receiver parity circuit counts ones received, including the parity bit. if the result is odd, a "0" appears in the 32nd bit. once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). depending on the state of control register bits cr2, and cr6 through cr8, the received 32-bit arinc word is then checked for correct decoding and label match before it is loaded into the 32 x 32 receive fifo. arinc words that do not match required 9th and 10th arinc bit and do not have a label match are ignored and are not loaded into the receive fifo. the table below describes this operation. data bit rate min data bit rate max high speed low speed receiver parity retrieving data functional description (cont.) hi-3588 the hi-3588 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 30v for the worst case condition (3.15v supply and 13v signal level). design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal (including nulls) is outside the differential voltage ranges, the hi-3588 receiver rejects the data. figure 2 is a block diagram showing receiver logic. the arinc 429 specification defines the following timing toler- ances for received data: 100k bps 1% 12k -14.5k bps 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 to 41.7 sec the hi-3588 accepts signals within these tolerances and rejects signals outside these tolerances. receiver logic achieves this as described below: 1. an accurate 1mhz clock source is required to validate the receive signal timing. less than 0.1% error is recommended. 2. the receiver uses three separate 10-bit sampling shift reg- isters for ones detection, zeros detection and null detection. when the input signal is within the differential voltage range for any shift register?s state (one zero or null) sampling clocks a high bit into that register. when the receive signal is outside the differential voltage range defined for any shift reg- receiver logic operation bit timing bit rate pulse rise time pulse fall time pulse width high speed low speed 0 x 0 x load fifo 1 no 0 x ignore data 1 yes 0 x load fifo 0 x 1 no ignore data 0 x 1 yes load fifo 1 yes 1 no ignore data 1 no 1 yes ignore data 1 no 1 no ignore data 1 yes 1 yes load fifo cr2 arinc word cr6 arinc word fifo matches bits 10, 9 enabled match cr7,8 label arinc 429 receiver arinc bus interface figure 1 shows the input circuit for the arinc 429 line receiver. the arinc 429 specification requires the following detection levels: one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts state differential voltage differential amplifiers comparators figure 1. arinc receiver input rina-40 rina rinb rinb-40 vdd gnd vdd gnd one null zero holt integrated circuits 5
hi-3588 fifo load control control bits cr2, cr6-8 / spi interface 32 bit shift register control bits cr0, cr1 clock option clock bit counter and end of sequence parity check 32nd bit data bit clock word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos label / decode compare 256-bit label look-up table 32x32 fifo rflag sck cs si so aclk figure 2. receiver block diagram once a valid arinc word is loaded into the fifo, the eos signal clocks the data ready flip-flop to a "1" and status register bit 0 (sr0) to a ?0?. the sr0 bit remains low until the receive fifo is empty. each received arinc word is retrieved via the spi interface using spi instruction 08 hex to read a single word, or 09 hex to empty the entire receive fifo. up to 32 arinc words may be held in the receive fifo. status register bit 2 (sr2) goes high when the receive fifo is full. failure to unload the receive fifo when full causes additional received valid arinc words to overwrite receive fifo location 32. a fifo half-full flag (sr1) is high when the receive fifo contains 16 or more arinc words. sr1 may be interrogated by the system?s external microprocessor, allowing a 16 word data retrieval routine to be performed. label recognition the user loads the 256-bit label look-up table to specify which 8-bit incoming arinc labels are captured by the receiver, and which are discarded. setting a ?1? in the look-up table enables processing of received arinc words containing the corresponding label. a ?0? in the look-up table causes discard of received arinc words containing the label. the 256-bit look-up table is loaded using spi op codes 02 hex, 03 hex or 06 hex, as described in table 1. after the look-up table is initialized, set control register bit cr2 to enable label recognition. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. if label recognition is enabled, the receiver compares the label in each new arinc word against the stored look-up table. if a label match is found, the received word is processed. if no match occurs, the new arinc word is discarded and no indicators of received arinc data are presented. the contents of the label look-up table may be read via the spi interface using instruction 0d hex as described in table 1. the hi-3588 has two sets of line receiver input pins, rina/b and rina/b-40. only one pair may be used to connect to the arinc 429 bus. the unused pair must be left floating. the rina/b pins may be connected directly to the arinc 429 bus. the rina/b-40 pins require external 40k ohm resistors in series with each arinc input. these do not affect the arinc receiver thresholds. by keeping excessive voltage outside the device, this option is helpful in applications where lightning protection is re- quired. when using the rina/b-40 pins, each side of the arinc bus must be connected through a 40k ohm series resistor in order for the chip to detect the correct arinc levels. the typical 10 volt dif- ferential signal is translated and input to a window comparator and latch. the comparator levels are set so that with the external 40k ohm resistors, they are just below the standard 6.5 volt mini- mum arinc data threshold and just above the standard 2.5 volt maximum arinc null threshold. reading the label look-up table line receiver input pins functional description (cont.) holt integrated circuits 6
hi-3588 master reset (mr) assertion of master reset causes immediate termination of data reception. the receive fifo, status register fifo flags and the fifo status rflag pin is also cleared. the control register is not affected by master reset. timing diagrams serial output timing diagram cs sck so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance serial input timing diagram cs sck si chh t ceh t msb ces t ds tt dh lsb cph t sckr t sckf t data rate - example pattern txaout arinc bit txbout null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 receiver operation rflag arinc data cs si bit 31 bit 32 rflg t arinc word 1 spif t so spi instruction 08h, (or 09h) (arinc word 2) (arinc word 3) rxr t functional description (cont.) cyc t cyc t holt integrated circuits 7
dc electrical characteristics v = 3.3v or 5.0v , gnd = 0v, ta = operating temperature range (unless otherwise specified). dd hi-3588 absolute maximum ratings supply voltages v ......................................... -0.3v to +7.0v voltage at pins rin1a, rin1b, rin2a, rin2b ..... -29v to +29v voltage at any other pin ............................... -0.3v to v +0.3v solder temperature (leads) .................... 280 for 10 seconds (package) .......................................... 220 dd dd c c power dissipation at 25c plastic quad flat pack ..................1.5 w, derate 10mw/ c dc current drain per pin .............................................. 10ma operating temperature range (industrial): .... -40c to +85c (hi-temp): .....-55c to +125c storage temperature range ........................ -65c to +150c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. logic outputs operating voltage range operating supply current output voltage: logic "1" output voltage v i = -100 a v logic "0" output voltage v i = 1.0ma v output current: output sink i v = 0.4v 1.6 ma (all outputs & bi-directional pins) output source i v = v - 0.4v -1.0 ma output capacitance: c 15 pf vdd 3.15 5.25 v vdd i 2.5 7 ma oh oh ol ol ol out oh out dd o dd 90%vdd 10% vdd limits parameter conditions unit symbol differential input voltage: one v common mode voltages 6.5 10.0 13.0 v (rin1a to rin1b, rin2a to rin2b) zero v less than 30v with -13.0 -10.0 -6.5 v null v respect to gnd -2.5 0 2.5 v input resistance: differential r - 140 - k to gnd r - 140 - k to v r - 100 - k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf (guaranteed but not tested) to gnd c 20 pf to v c 20 pf input voltage: input voltage hi v v input voltage lo v v input current: input sink i 1.5 a input source i -1.5 a min typ max arinc inputs - pins rina, rinb, rina-40 (with external 40kohms), rinb-40 (with external 40kohms) logic inputs ih il nul i g dd h ih il i g dd h ih il ih il (rina to rinb) pull-down current (mr, si, sck, aclk pins) i 250 600 a pull-up current ( pin) i -600 -300 a 80% vdd 20% vdd pd pu cs holt integrated circuits 8
ac electrical characteristics hi-3588 ordering information hi - 3588 xx x x package description 44 pin plastic chip-scale, qfn (44pcs) part number pc 44 pin plastic quad flat pack, pqfp (44ptqs) pq lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank temperature range burn in -40c to +85c no -55c to +125c no t part number t i flow i the hi-3588pci and hi-3588pct use a 44-pin plastic chip-scale package. this package has a metal heat sink pad on its bottom surface that is electrically connected to the die. for the hi-3588, the primary advantage of this package is its small size; heat sinking provides little benefit because hi-3588 dissipation is low. if connected, the heat bottom sink pad should be connected to vdd. do not connect heat sink pad to gnd. heat sink - chip-scale package only limits parameter symbol units min typ max spi interface timing receiver timing sck clock period active after last sck rising edge t 20 ns setup time to first sck rising edge t 10 ns hold time after last sck falling edge t 40 ns inactive between spi instructions t delay - last bit of received arinc word to rflag(full or empty) - hi speed t 16 s received data available to spi interface. rflag to active spi receiver read or clear fifo instruction to rflag t t 200 ns 35 ns spi si data set-up time to sck rising edge t 30 ns spi si data hold time after sck rising edge t 30 ns sck rise time t 10 ns sck fall ime t 10 ns sck pulse width high t 90 ns sck pulse width low t 80 ns so valid after sck falling edge t 130 ns so high-impedance after sck falling edge t 100 ns delay - last bit of received arinc word to rflag(full or empty) - lo speed t 126 s t0 ns 155 ns cyc cph ds dh sckr sckf sckh sckl dv chz rflg rxr cs cs cs cs cs chh ces ceh rflg spif vdd = 3.3v or 5.0v, gnd = 0v, ta = operating temperature range and fclk=1mhz 0.1% with 60/40 duty cycle + holt integrated circuits 9
revision history revision date description of change ds3588, rev. new 05/08/08 initial release rev. a 10/10/08 revised ac electrical characteristics rev. b 05/22/09 clarified relationship between spi bit order and arinc 429 bit order rev. c 07/02/09 removed references to v+, v-, which are not connected on this device holt integrated circuits 10 hi-3588
hi-3588 package dimensions 44-pin plastic chip-scale package (qfn) package type: 44pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .203 .006 (5.15 .15) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .203 .006 (5.15 .15) typ typ bottom view top view bsc .276 (7.00) bsc max inches (millimeters) heat sink pad on bottom of package. heat sink must be left floating or connected to vdd. do not connect to gnd. package type: 0 7 detail a see detail a sq. 44ptqs 44-pin plastic quad flat pack (pqfp) .006 (.15) .547 .010 (13.90 .25) .394 .004 (10.0 .10) sq. max. .014 ..002 (.35 .05) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .055 .002 (1.4 .05) .063 (1.6) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 11

▲Up To Search▲

Price & Availability of HI-3588PQI

	To Download HI-3588PQI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .